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ocr_text: Lithography Technology Requirements\nYEAR OF PRODUCTION [ 2018 | 2020 | 2022 | 2025 | 2028 | 2031 | 2034\nMPU / Logic\nLogic industry "Node Range” Labeling (nm, [ v7" [ "6" [ "3" [ "24" | "1.6" ["1.0eq”["07eq"\nEPE, Single Exposure for <36nm pitch, Cost of EUV patterning\nIMPU/ASIC Minimum Metal % pitch (nm, ETE CEE\n[Metal CD control (3 sigma) (nm, 2.7 1.8 1.6\n|Contacted poly half pitch (nm, [270 | 240 | 225 | 21.0 | 200 | 200 | 200\n[Physical Gate Length for HP Logic (nm, [20 | 18 | 16 [| 1a | 12 | 12 [| 12\nGate LER (nm, [ 08 [07 [ 06 |\n|Overlay (3 sigma) (nm, [36 | 30 | 24 21\nIMPU/ASIC finFET fin minimum 1/2 pitch (nm) | 16.0 | 140 | 120 |= | [~~ | ~~ |\n[FinFET Fin width (nm) ____ [ 80 [ 70 eo | |\n[Fin CD control (3 sigma) (nm, [ogo [070 [060 [| | [|]\nLateral Gate All Around (LGAA) 1/2 pitch EE 11 | 10 | 10 10\nLGAA minimum width || CC\nILGAA CD control (3 sigma) (nm, | — |\nGAA LER (nm, | | ——\nIMPU/ASIC minimum contact hole or via pitch (nm) | 51 | 42 | 34 | 30 | 23 23 23\n\Via CD after etch (nm) [18 [15 12\n[Contact CD (nm)after etch - finFET, LGAA ETE 167% FN [° 1607 3° 460” |
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