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ocr_text: Aspect Ratio Trapping\n» ART has been developed to integrate Ge or III-V devices with CMOS: the buffer layer is\nthin (< 1 pm) to allow a standard CMOS back-end process, the technique has a low thermal\nbudget, and the process can be applied to large wafers to allow integration into a CMOS process.\n> Ge or III-V material is epitaxially grown in Ge\nin dielectric layers on silicon. | ie\nIn ART, dislocations are guided to the ’\n== dielectric sidewalls\nand trapped, producing a low-dislocation silicon 200m\nregion at the top of the trench. —_—\n(a) (b)\nFigure 1. Depiction of Aspect Ratio Trapping using Ge in SiO; trenches. (a) XTEM of\n» Typically, the trenches are formed in (xin syn 0s is, Del mel eC te\nthermally-grown SiO, by lithography & RIE i, «ideal. yielding a region a the op of the trench with low dislocation deni. (by\netching (in the fig., they are A depiction of a Ge or ITI-V MOSFET using ART.\n800 nm deep, 200 nm wide and millimeters long). [J. G. Fiorenza et al., ECS Transactions, 33 (6) 963-976 (2010)]
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