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ocr_text: . Gate-Source VoltageV8s  pryin-Source Voltage,\n» If a CMOS technology generation has: wo Cae SS capacitance,\n- a minimum channel length and width (L & W), FH i eS)\n- an oxide thickness to, : i 8\n- a substrate doping Na, lL == |\n- a power supply voltage Vpp,\n- a threshold voltage Vy, etc. ——\nOriginal device \ Wiring Scaled device\n» Downscaling of the gate length and width, [™S (Wiring |\noxide thickness, junction depth, and he W tod Lor\nsubstrate doping. | Gate | es [Ga] lo\n==) Supply and threshold voltages are also [mS Ls) SU es\nscaled by a factor of y. Twa She\nThe electric field is constant\n(rules developped by Robert Dennard in\n1974).\nThe transistor density is increased by\nfactor of y2. P—
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