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body_diff: "[{\"diffs\":[[1,\"<html>\\\r\\\n<head>\\\r\\\n  <title>[分享] TSMC Wafer 的良率模拟计算 (重发)</title>\\\r\\\n  <basefont face=\\\"微软雅黑\\\" size=\\\"2\\\" />\\\r\\\n  <meta http-equiv=\\\"Content-Type\\\" content=\\\"text/html;charset=utf-8\\\" />\\\r\\\n  <meta name=\\\"exporter-version\\\" content=\\\"YXBJ Windows/608924 (zh-CN, DDL); Windows/10.0.0 (Win64); EDAMVersion=V2;\\\"/>\\\r\\\n  <meta name=\\\"content-class\\\" content=\\\"yinxiang.peso.rte\\\"/>\\\r\\\n  <style>\\\r\\\n\\tbody, td {\\\r\\\n\\t  font-family: 微软雅黑;\\\r\\\n\\t  font-size: 12pt;\\\r\\\n\\t}\\\r\\\n  </style>\\\r\\\n</head>\\\r\\\n<body>\\\r\\\n<a name=\\\"31415\\\"></a>\\\r\\\n<h1>[分享] TSMC Wafer 的良率模拟计算 (重发)</h1>\\\r\\\n\\\r\\\n<div><span><div>智能摘要</div><div>[分享] TSMC Wafer 的良率模拟计算(重发)原创 Ryan 火红的兔子收录于合集#知识4个#芯片3个#dft3个##WAFRT1个## Yield2个巴勒斯坦人民需要正义分享一个网站在线计算wafer 良率相关的图形和数据。https:wafercalculator.com例如下图模拟计算了Zen 2芯片的尺寸在7nm工艺条件下的wafer 良率的图形和相关数据。对比地下图模拟计算了Zen 2芯片的尺寸在早期5nm工艺条件下的wafer 良率的图形和相关数据。如何使用例子:2019年12月,台积电宣布其芯片尺寸为17.92 mm 2的5 nm测试芯片的平均良率约为80%,单片峰值良率超过90%。</div><div>原文约 2112 字  | 图片 24 张 | 建议阅读 3 分钟</div><h1> [分享] TSMC Wafer 的良率模拟计算 (重发) </h1><div>原创 Ryan  火红的兔子 </div><div><br/></div><div>收录于合集</div><div>#知识4个</div><div>#芯片3个</div><div>#dft3个</div><div>##WAFRT1个</div><div>## Yield2个</div><img src=\\\":/b6e6b2de642a4d03867d2508681da8ac\\\" type=\\\"image/gif\\\" data-filename=\\\"Image.gif\\\" style=\\\"--en-uploadstate:uploaded;\\\"/><p>巴勒斯坦人民需要正义</p><img src=\\\":/21bfce92cb2d4118bf85d235e6234b15\\\" type=\\\"image/png\\\" data-filename=\\\"Image.png\\\" style=\\\"--en-uploadstate:uploaded;\\\"/><div>    </div><div>分享一个网站在线计算wafer 良率相关的图形和数据。</div><p>  </p><p>   <b>  https://wafercalculator.com/</b></p><p>例如下图模拟计算了Zen 2芯片的尺寸在7nm工艺条件下的wafer 良率的图形和相关数据。</p><img src=\\\":/d5c4bd7dc0ca4d8aae2e24b2f4d80d0d\\\" type=\\\"image/png\\\" data-filename=\\\"Image.png\\\" style=\\\"--en-uploadstate:uploaded;\\\"/><p>对比地下图模拟计算了Zen 2芯片的尺寸在早期5nm工艺条件下的wafer 良率的图形和相关数据。</p><img src=\\\":/22ee3d636142496da6b8239330e8f60e\\\" type=\\\"image/png\\\" data-filename=\\\"Image.png\\\" style=\\\"--en-uploadstate:uploaded;\\\"/><img src=\\\":/f2a1e79b933c4d29b332eee62bb574a9\\\" type=\\\"image/png\\\" data-filename=\\\"Image.png\\\" style=\\\"--en-uploadstate:uploaded;\\\"/><img src=\\\":/0c5cd73bb2eb417ab0c0179dbb209449\\\" type=\\\"image/gif\\\" data-filename=\\\"Image.gif\\\" style=\\\"--en-uploadstate:uploaded;\\\"/><div><b>如何使用</b></div><img src=\\\":/d7992258192e49a1b7c35dcf948d7b09\\\" type=\\\"image/png\\\" data-filename=\\\"Image.png\\\" style=\\\"--en-uploadstate:uploaded;\\\"/><p><b><u>例子：2019年12月，台积电宣布其芯片尺寸为17.92 mm 2的5 nm测试芯片的平均良率约为80%，单片峰值良率超过90% 。</u></b></p><p>    Using the calculator, a<b>300 mm wafer w</b>ith a<b>17.92 mm2</b>die would produce <b>3252</b> dies per wafer. An<b> 80% yield</b> would mean<b> 2602 good dies</b> per wafer, and this corresponds to a <b>defect rate</b> of <b>1.271# per sq cm.</b></p><p>根据上述计算信息，打开这个网站，如下图所示，近似地填写信息如下：</p><p><b>  Die width = 4.3mm</b></p><p><b>  Die Height = 4.165 mm</b></p><p><b>  Scribe Lane X = 165um</b></p><p><b>  Scribe Lane XY= 205um</b></p><p><b>  Wafer为12英寸，300mm</b></p><p><b>  Defect Density = 1.271 </b>（良率模型反推）</p><div><i>Note：分割道一般100um的量级，对max Dies有一定影响。</i></div><p><i>          Edge Loss 对大size的Dies count会有一些影响，3mm左右设置也比较合理。就是Wafer边缘那一圈看起来像是被磨过的偏银色边缘部分，如下图。</i></p><img src=\\\":/ebac93fa47c3422ca3cdb2065b94e3a3\\\" type=\\\"image/png\\\" data-filename=\\\"Image.png\\\" style=\\\"--en-uploadstate:uploaded;\\\"/><p><b>OK，来打开网页，输入上述参数信息，得到的wafer map如下：</b></p><img src=\\\":/2a9b1dcd26654daca565f45d8338d2b6\\\" type=\\\"image/png\\\" data-filename=\\\"Image.png\\\" style=\\\"--en-uploadstate:uploaded;\\\"/><p><b><u>例2：Xbox Series X SoC. Microsoft used TSMC’s best DUV-only 7nm (N7) process node, which had been stated as having a defect rate of 0.09 defects per square centimeter.</u></b></p><img src=\\\":/f262982b85f84eeeb5db8b0210bb70a5\\\" type=\\\"image/png\\\" data-filename=\\\"Image.png\\\" style=\\\"--en-uploadstate:uploaded;\\\"/><p>良率信息计算如下：</p><ul><li><div><br/></div><p><i>A 300 mm wafer has 706.86 cm2 of area</i></p></li><li><div><br/></div><p>A defect rate of 0.09 defects per cm2 means ~64 defects per wafer</p></li><li><div><br/></div><p>Scarlett is 360.4 mm2 (15.831 mm x 22.765 mm)</p></li><li><div><br/></div><p>Note that SoCs are rectangles, and wafers are circular,</p></li><li><div><br/></div><p>Wafer die calculators show that 100% yield of this SoC size would give 147 dies per wafer</p></li><li><div><br/></div><p>Microsoft sets the frequency/power such that if all dies are good, all can be used</p></li><li><div><br/></div><p>With a 0.09 / cm2 defect rate, there are 107 good dies per wafer</p></li><li><div><br/></div><p>This means a 73% yield, 107 / 147</p></li></ul><img src=\\\":/c25a771dcf484d97949aa34913addaf7\\\" type=\\\"image/png\\\" data-filename=\\\"Image.png\\\" style=\\\"--en-uploadstate:uploaded;\\\"/><div><i>PART</i></div><div><i>01 良率计算公式</i></div><img src=\\\":/87fa66bc21cc48b589c6d278f163dc07\\\" type=\\\"image/gif\\\" data-filename=\\\"Image.gif\\\" style=\\\"--en-uploadstate:uploaded;\\\"/><p>    良率计算模型有以下几种：</p><p><ins lang=\\\"EN-US\\\" style=\\\"background-color:;color:;\\\">     </ins></p><img src=\\\":/5d647209555b44d2963f1739a45c7eff\\\" type=\\\"image/png\\\" data-filename=\\\"Image.png\\\" style=\\\"--en-uploadstate:uploaded;\\\"/><p><ins lang=\\\"EN-US\\\" style=\\\"background-color:;color:;\\\">    </ins></p><div><ins lang=\\\"EN-US\\\" style=\\\"background-color:;color:;\\\">   有人疑问模型怎么这么多种？ 那你应该很容易反推一个隐藏的信息，没有一个完美描述良率的全能公式，所以才会有这么多yield model， 因此不需要对此保持疑问，在不同的良率提升阶段，适用不同的公式描述与Die Size的关系。</ins></div><p><br/></p><img src=\\\":/9115ba23832e43378526698a3de47ecf\\\" type=\\\"image/png\\\" data-filename=\\\"Image.png\\\" style=\\\"--en-uploadstate:uploaded;\\\"/><p>ITRS建议的一种Negative binomial 和 alpha 参数值：</p><img src=\\\":/3665a2db9e9d4f5ba552d02b0acdc0dc\\\" type=\\\"image/png\\\" data-filename=\\\"Image.png\\\" style=\\\"--en-uploadstate:uploaded;\\\"/><img src=\\\":/861e94634c514ea0b54848f41cd095d7\\\" type=\\\"image/gif\\\" data-filename=\\\"Image.gif\\\" style=\\\"--en-uploadstate:uploaded;\\\"/><div><i>PART 02  TSMC 5nm 趋势与D0</i></div><img src=\\\":/db644d1ffd2f4b0991b31076651bfd03\\\" type=\\\"image/gif\\\" data-filename=\\\"Image.gif\\\" style=\\\"--en-uploadstate:uploaded;\\\"/><img src=\\\":/39f456feaf2f49e9ba714ff16e7b5b22\\\" type=\\\"image/png\\\" data-filename=\\\"Image.png\\\" style=\\\"--en-uploadstate:uploaded;\\\"/><img src=\\\":/fe3dd0792a7e42cabf8c2303531ea4c5\\\" type=\\\"image/png\\\" data-filename=\\\"Image.png\\\" style=\\\"--en-uploadstate:uploaded;\\\"/><p>  通常，DD 每平方厘米低于0.5的数值都是一个不错的指标，我们曾看到台积电在其N7工艺节点上，仅在高产量（HVM）制造后的三个季度内，便取得了DD=0.09/cm2的数据，而5NM工艺节点的缺陷率通常会与开发过程中的前一个节点(7nm)的缺陷率进行比较。</p><p> </p><img src=\\\":/38f823519ab54f3688f74290ef392114\\\" type=\\\"image/png\\\" data-filename=\\\"Image.png\\\" style=\\\"--en-uploadstate:uploaded;\\\"/><p>  </p><p>台积电目前的 N5 工艺在开发周期中的缺陷密度比同时期的 N7 工艺要低:</p><img src=\\\":/1d4e347da8fe4be897cbfa729acfaec6\\\" type=\\\"image/png\\\" data-filename=\\\"Image.png\\\" style=\\\"--en-uploadstate:uploaded;\\\"/><p>台积电的 N5 工艺在2020年底的每平方厘米的缺陷数约为 0.10 至 0.11 个，随后续的大批量生产，缺陷数应该降至 0.10 以下。</p><p>  5nm 良率略高的部分原因可能是极紫外(EUV) 技术的使用增加，该技术减少了制造步骤总数。每个步骤都有可能降低良率，因此通过将 4 步 DUV 替换为 1 步 EUV，可以消除部分缺陷率。</p><img src=\\\":/d45a4926446149dda509a16a96b99301\\\" type=\\\"image/png\\\" data-filename=\\\"Image.png\\\" style=\\\"--en-uploadstate:uploaded;\\\"/><img src=\\\":/c27c8bdc82684c4caf44beba2def5ca1\\\" type=\\\"image/png\\\" data-filename=\\\"Image.png\\\" style=\\\"--en-uploadstate:uploaded;\\\"/><img src=\\\":/740bbea47f9941c0aee91dd0da433936\\\" type=\\\"image/png\\\" data-filename=\\\"Image.png\\\" style=\\\"--en-uploadstate:uploaded;\\\"/><p>癸卯年【兔年】</p><p>壬戌月戊申日</p><p>2023 .10.17</p><p>17</p><p>宜</p><div> </div><p>开心 欢乐</p><p>忌</p><div> </div><p>猜疑 生气</p><p>“致良知，当如登高山，不可直上，须弯道而行” - 王阳明</p><p> Ryan</p></span>\\\n</div></body></html>\\u0000\"]],\"start1\":0,\"start2\":0,\"length1\":0,\"length2\":7167}]"
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